Event Name 2008 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

The growing complexity and shrinking geometries of modern device technologies are making these high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concern about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). Papers that cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes, along with case studies will be presented.

Key Dates

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Advance Registration Deadline: March 11th, 2009!

The Venue

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Schwab Residential Center at Stanford University. http://www.selse.org/local.html

Workshop Registration

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Conference location and hotel information is available http://www.selse.org/local.html

Advance Program

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Tuesday -- Wednesday

March 24, 2009 (Tuesday)

8:00 AM - 8:45 AM CONTINENTAL BREAKFAST & Registration

8:45 AM - 9:00 AM	OPENING SESSION
	Welcome and Introduction from General Co-Chair and Committee

9:00 AM - 10:30 AM	Session 1 - System Vulnerability and Workload Effects Chair: TBD
	The Effect of Input Data on Program Vulnerability Vilas Sridharan and David Kaeli
	Quantized AVF: A Means of Capturing Vulnerability Variations over Small Windows of Time Arijit Biswas, Niranjan Soundararajan, Shubhendu Mukherjee and Sudhanva Gurumurthi
	Soft Error Effect and Register Criticality Evaluations: Past, Present and Future Régis Leveugle, Laurence Pierre, Paolo Maistri and Renaud Clavel

10:30 AM - 10:45 AM BREAK

10:45 AM - 12:15 PM	Session 2 - Applications / Case Studies Chair: TBD
	Evaluation of Low-Cost Detection and Recovery of Soft Errors in an ABS controller Daniel Skarin and Johan Karlsson
	A Case Study of the Soft Errors Observed in I/O Adapters Anh Dang, Pia Sanda, Ricardo Mata and Subhasish Mitra
	System Design Enhancement and Validation Using Neutron Beam Testing Tsu-Yau Chuang, Eric Schmidt and Shi-Jie Wen

12:15 PM - 12:45 PM LUNCH

12:45 PM - 2:00 PM	Poster Session 1
	Adapting to Variation in Latch SEU Rates Kenneth Zick and John Hayes
	Implementation and Validation of a Low-Cost Single-Event Latchup Mitigation Scheme Michael Nicolaidis, Kholdoun Torki, Federico Natali, Kader Belhaddad and Dan Alexandrescu
	Testing the Critical Operating Point (COP) Hypothesis using FPGA Emulation of Timing Errors in Overscaled Soft-Processors Sriram Narayanan, Galen Lyle, Rakesh Kumar and Douglas L. Jones
	Thermal Management in Reliably Overclocked Systems Prem Kumar Ramesh, Viswanathan Subramanian and Arun Somani
	Analysis of a Multiple Cell Upset Failure Model for Memories Sanghyeon Baeg, Pedro Reviriego, Juan Antonio Maestro, ShiJie Wen and Richard Wong

2:00 PM - 2:15 PM BREAK

2:15 PM - 4:15 PM	Session 3 - SER Measurement and Modeling Chair: TBD
	Neutron Beam Irradiation Study of Workload Dependence of SER in a Microprocessor Ted Hong, Sarah Michalak, Todd Graves, Jerry Ackaret, Sonny Rao, and Subhasish Mitra
	Trends from Nine Years of Soft Error Experimentation. Anand Dixit, Raymond Heald and Alan Wood
	Comparison of Alpha-particle and Neutron-induced Combinational and Sequential Logic Error Rates at the 32nm Technology Node Balkaran Gill, Norbert Seifert and Victor Zia
	Single-Threaded Mode Architectural Vulnerability Prediction During Redundant Execution Blake C. Sutton and Sudhanva Gurumurthi
	Soft-Error Cross-Section Mapping and Rate Prediction using Accurate Simulation Klas Lilja

4:15 PM - 4:30 PM BREAK

4:30 PM - 5:15 PM	Panel - “Standards for SER in System Components”

5:15 PM - 6:00 PM	Birds of a Feather Sessions Participants Divide into Groups to Discuss a Question
	Microprocessors Small Systems Large Systems

6:00 PM DINNER & RECEPTION

March 25, 2009 (Wednesday)

7:45 AM - 8:30 AM CONTINENTAL BREAKFAST

8:30 AM - 9:15 AM	Report From Birds of Feather Sessions

9:15 AM - 10:15 AM	Session 4 - Mitigation Techniques – Logic Chair: TBD
	A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability Dawood Alnajjar, Younghun Ko, Takashi Imagawa, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi and Takao Onoye
	Fault-Tolerant Resynthesis for Dual-Output LUTs Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He and Minming Li

10:15 AM - 10:30 AM BREAK

10:30 AM - 12:00 PM	Session 5 - Microprocessors Chair: TBD
	A Low-Overhead Technique to Protect the Issue Control Logic Against Soft Errors Javier Carretero, Xavier Vera, Jaume Abella, Pedro Chaparro and Antonio González
	Voltage Noise: Why It’s Bad, and What To Do About It Vijay Janapa Reddi, Meeta S. Gupta, Krishna K. Rangan, Glenn Holloway, Gu-Yeon Wei, Michael D. Smith and David Brooks
	A Detector for Harmful Errors Jing Yu and Maria Garzarán

12:00 PM - 12:45 PM LUNCH

12:45 PM - 2:00 PM	Poster Session 2
	NBTI-Aware Dynamic Instruction Scheduling Taniya Siddiqua and Sudhanva Gurumurthi
	Exploring the Synergy of Emerging Workloads and Silicon Reliability Trends Marc de Kruijf and Karu Sankaralingam
	A Foundation for the Accurate Prediction of the Soft Error Vulnerability of Scientific Applications Greg Bronevetsky, Bronis R. de Supinski and Martin Schulz
	Soft-error Mitigation at the Architecture-Level Using Berger Codes and Instruction Repetition Daniel Limbrick, Edward Ossi, Bharat Bhuva and William Robinson
	3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits Rajesh Garg and Sunil Khatri

2:00 PM - 2:15 PM BREAK

2:15 PM - 3:00 PM	Invited Talk: “On The Accuracy of Accelerated and Life Soft Error Testing" Helmet Puchner, Cypress Semiconductor

3:00 PM - 4:30 PM	Session 4 - VI: Mitigation Techniques – Arrays and Sequentials Chair: TBD
	Soft Error Mitigation Schemes for High Performance and Aggressive Designs Naga Durga Prasad Avirneni, Viswanathan Subramanian and Arun Somani
	Protecting Prediction Arrays against Faults Yiannakis Sazeides, Costas Kourouyiannis, Nikolas Ladas and Veerle Desmet
	Modeling SRAM Failure Rates to Enable Fast, Dense, Low-Power Caches Jangwoo Kim, Mark McCartney, Ken Mai and Babak Falsafi

4:30 PM - 4:45 PM BREAK

4:45 PM - 5:15 PM	CLOSING DISCUSSION

More Information

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General Information

Alan Wood
General Chair
E-Mail: alanw@ieee.org

Committees

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Organizing Committee

General Chair
Alan Wood, Sun

Program Chairs
Allan Silburt, Cisco
Adrian Evans, Cisco
Jim Tschanz, Intel

Past Chairs
Wendy Bartlett, HP
Babak Falsafi, CMU

Finance Chair
Vikas Chandra, ARM

Publications Chair
Norbert Seifert, Intel

Web Publicity Chair
Jeff Wilkinson, Medtronic

Publicity Chair
Vivian Zhu, TI

Local Arrangements Chair
Subashish Mitra, Stanford

For more information, visit us on the web at: http://www.selse.org

The 2009 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE2009 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).